1. Technical Field
The present invention relates generally to power management for the software systems of portable or mobile devices. In particular, the present invention provides a method and apparatus for using low power states of a processor to extend battery life.
2. Description of Related Art
Mobile and wireless communications technologies have given rise to the proliferation of handheld and portable devices with computing capabilities, such as, for example, personal digital assistants and pocket computers. Devices such as these use small batteries for their operation instead of direct connections to power supplies. Because the batteries of portable and mobile devices tend to discharge relatively quickly, energy consumption and power management are key considerations in the design of such devices.
Some devices incorporate system-on-a-chip microprocessors that provide advanced integrated power management. In such systems, the processor is put into a low power state when no applications are active and when no tasks or interrupt routines need servicing. One of the most commonly used low power states is referred to as the “idle” state. When the processor is in idle state it stops executing instructions. The processor may be reactivated or brought out of idle upon the occurrence of some event, such as the expiration of a hardware timer, or the detection of a keyboard press or other hardware interface interrupt. The event or interrupt causes the processor to transition out of the low power state and service the interrupt. By putting the processor into the idle state, battery life may be extended, particularly in systems in which the power consumed by the processor is significant compared to that of other components such as display and memory components.
Known system-on-a-chip microprocessors include the Cirrus Logic® EP7211 microprocessor, available from Cirrus Logic, Inc., and the Intel® StrongARM SA1100 microprocessor, available from Intel Corporation. These processors find widespread application in high-end mobile and portable products. Processors such as the EP7211 and SA1100 have an operating state, wherein the device operates at full performance, and two low power states, which will be referred to herein as IDLE and SLEEP states. In IDLE state, the clock to the central processing unit (CPU) core is halted while awaiting an event such as a keyboard press to generate an interrupt. In SLEEP state, on the other hand, the clock to most of the peripheral functional blocks on the chip is further stopped. An event such as a keyboard press, however, can wake up the processor from SLEEP state.
Power consumption for system-on-a-chip microprocessors varies considerably depending upon the processor's power state. Typical rates of power consumption for the Cirrus Logic® EP7211, for example, are 40 milliwatts (mW) in OPERATION state (with an 18 megahertz (MHz) CPU clock), 15 mW in IDLE state (18 MHz CPU clock), and 0.012 mW in SLEEP state. As these rates indicate, SLEEP state enables the processor to consume comparatively little power.
In a system that spends most of its time idling, it may be desirable to take advantage of SLEEP state, reduce power consumption, and thereby extend battery life. Current operating systems, however, take advantage of SLEEP state in only two situations, namely: (1) when the user powers off the device; and (2) whenever the high-level power management function determines that the device should be turned off, for example, due to user inactivity. Known devices such as Compaq Computer Corporation's Itsy Pocket Computer and the Palm™ Pilot, by way of example, implement SLEEP state in these ways. Known operating systems do not take advantage of the low power consumption of SLEEP state while the system is on. Instead, current operating systems use IDLE state to reduce power consumption while the system is on, as explained below. If a system is not being actively used by a user while the device is on, however, a great deal of battery power is wasted while the processor sits in IDLE state. Thus, a need exists for the ability to put a processor in SLEEP state, with its comparatively low power consumption, while the system is in use, to conserve battery power.
Known devices, operating systems and processors do not exercise SLEEP state in place of IDLE state, and the reason is partly due to the relatively long amount of time it takes for the processor to transition out of SLEEP state. The transition time for the EP7211 processor to come out of SLEEP state, for example, may be as long as 250 milliseconds (msec). The StrongARM SA 1100 exhibits transition times that range from 10 msec to 160 msec. Transitioning out of IDLE state, on the other hand, takes only a few CPU clock cycles, i.e., comparatively little time. The length of the transition time out of SLEEP state is critical in view of one of the most basic features of practically any operating system (OS): namely, the periodic timer interrupt. The timer interrupt is used for updating kernel time, process/task times, check queues and running the software timer call back list. The detailed operation of the timer interrupt is known to anyone skilled in the art of systems programming. Typically, the OS timer interrupt interval ranges from 1 msec to 50 msec. The sum of the time deviations associated with transitioning into and out of a low power mode (i.e., the total transition time) must be smaller than the timer interrupt interval. For example, suppose an OS is expected to be interrupted 100 times per second by a timer interrupt, i.e., the interrupt interval is 10 msec, but the total low power transition time is more than 10 msec. In this case, the internal time keeping would be severely compromised, since the interrupt no longer represents a 10 msec time lapse, as assumed by the kernel. Similarly, the updating of process times would be incorrect, as this is also based on the assumption of a 10 msec time lapse.
To take advantage of the power savings offered by SLEEP state, it would be desirable to use an operating system or software system that is not compromised by the transition time delays associated with toggling low power states. One type of operating system that is able to handle this sort of time delay is one that incorporates a work dependent timing routine. The term “work dependent”, as used herein, means that the OS is interrupted only when there is work to be done, such as, for example, when the hardware timer expires or when the user makes a touchscreen press. A basic feature of a work dependent timing routine is the utilization of a dynamically adjustable timer interrupt interval, as opposed to a periodic timer interrupt interval. In a work dependent timing routine, the hardware timer is reprogrammed to interrupt the processor at a specific time in the future when the OS knows that work will need to be done. Thus, in an OS with a work dependent timing routine, the interval between timer interrupts may be quite large. If the interval is large enough, the processor could be put into SLEEP state between timer interrupts in order to achieve significant power savings without compromising the operation of the OS, or the functionalities of the system.
Further note that with a work dependent timing scheme, the energy consumed during execution of the timer interrupt handler associated with the skipped timer ticks is also saved. Also, any energy associated with transitioning into and out of a low power state in an OS with a periodic timing scheme is saved in those timer ticks that are skipped.
Although the concept of a work dependent timing scheme is known experimentally, to our knowledge there is no commercially available OS, including open source OSs such as Linux, that comes equipped with a work dependent timing scheme. Even more importantly, to our knowledge, the few experimentally known OSs that do implement a work dependent timing scheme exercise only one power management state, if any at all, namely the least efficient power management state. The present invention solves this problem and demonstrates how a multiple of power management states may be utilized.
Low power states cannot be exercised effectively in a dynamic fashion without addressing system timing behavior. Known embedded processors, however, such as the Cirrus Logic® EP7211 and the Intel® StrongARM 1110 microprocessors, disable their internal hardware timers when they are in SLEEP state. Thus, the internal hardware timer is not available to handle timing or power management functions while the processor is in SLEEP state. Some other timer source is therefore necessary. These processors have another timer source: a real-time clock (RTC). The RTC timers, however, tend to have poor resolution compared to that of internal timers. For example, the internal timer of the Cirrus Logic® EP7211 is capable of delivering timing intervals from 2 microseconds (μsec) to 32 seconds (sec), whereas the RTC timer has a minimum resolution of 1 sec. The present invention overcomes the timing resolution problem.
Certain RTCs, such as the Cirrus Logic® and Strong ARM RTCs, present another problem. Consider the Cirrus Logic® RTC, which has a 1-sec timing resolution. That RTC is capable of generating interrupts only on absolute whole-second boundaries. The boundaries, or phases, cannot be adjusted, i.e., shifted in time. Thus, it is not possible to program the RTC to generate an interrupt in precisely 2 seconds, for example, from the current instantaneous time. The present invention overcomes problems caused by the RTC phase.
A system that takes advantage of a low power state while the processor is still running must also be able to handle interrupts from other sources besides the hardware timer. The present invention solves the problem of handling interrupts while a system is in a low power state, wherein the interrupts may be random, such as those generated by a user, a network, a sensor, or the like.
It should be noted that most computing systems use non-aggressive power management schemes, if they use any at all. Such power management schemes are well known to those who, for example, use Windows®- or Intel®-based computers or laptops and are described, for example, in U.S. Pat. No. 6,065,123 to Chou et al. The computer system of the Chou et al patent uses a power management apparatus that must detect when the computer system is going to enter the Standby low power mode: more specifically, the apparatus of Chou et al waits until one of three events occurs—namely, a user command, an application command or an inactivity timeout event—to trigger a power-saving feature that places the system into Standby mode. The power-saving module, called the InstantON servicing agent, is loaded and executed only after the operating system (OS) of the Chou computer system has loaded and is running. As any other loadable and memory resident module, the InstantON agent must periodically be scheduled by the OS to run in order to be able to detect whether a request has been made to enter Standby mode. One consequence of persistently scheduling the power-saving module of Chou et al is that the InstantON agent uses up available processing bandwidth and power, in addition to what the OS itself is already consuming. Furthermore, the computational overhead and slowness associated with signaling a low power event to or scheduling the InstantOn agent will necessarily limit the Chou apparatus in its ability to enter a low power state in a speedy fashion.
In contrast to computer systems that use non-aggressive power management schemes, many devices today would benefit from a much more aggressive power management scheme that is an inherent and tightly integrated part of the OS and which automatically and instantaneously exploits opportunities to conserve power by entering low power states within extremely short timing intervals. For example, pervasive devices with limited energy supplies such as batteries have experienced a long-felt need for a power management implementation that executes instantaneously, with no impact on available processor bandwidth. In addition, it would be advantageous to provide a power management method or apparatus that takes into consideration the power consumption of a system when it is in a low power state and/or when the system enters or exits a low power state.
Consequently, there is a need for an operating system, software system and/or method which is capable of exercising various low power states in a rapid dynamic fashion and in coordination with other timing requirements of the system. The description of the invention which follows details how this may be achieved.
It should be pointed out that any operating system or software system that has large enough timer interrupt intervals, whether the system is work dependent or not, and whether the timer interrupt is periodic or not, may take advantage of the following invention.